Keynote by Giovanni DE MICHELI, EPFL-LSI/CSI, Switzerland
"Nanoelectronics: challenges and opportunities"
Absract - The scaling of CMOS technology is coming soon to an end, and yet it is unclear whether CMOS devices in the 10-20 nanometer range will find a useful place in semiconductor products. At the same time, new silicon-based technologies (e.g., silicon nanowires) and non-silicon based (e.g., carbon nanotubes) show the promise of replacing traditional transistors. In this scenario, there are multiple challenges to face, like the production of nanoscale CMOS with reasonable yield and reliability, the creation of newer circuit structures with novel materials as well as the mixing and matching of older and newer technologies in search of a good balance of costs and benefits.
Within this rich set of possibilities, opportunities will be driven by the ability of designing complex circuits with these technologies. Unprecedented problems related to defect density, failure rates, temperature sensitivity compensate the availability of an even larger number of devices. Our ability to define the right design technology and methodology will be key in the realization of products of these nanotechnology, and on the direction that the semiconductor road will take after the inevitable curve that is on the horizon.
Giovanni De Micheli
CSI - Professor and Director
INF 341, Station 14, EPF Lausanne
Tel: 41 21 693 0911
Fax: 41 21 693 0909
Keynote by Christian PIGUET, CSEM, Neuchâtel, Switzerland
"Static and dynamic power reduction by architecture selection"
Abstract - As leakage power and total power is a more and more dramatic issue is very deep submicron technologies, this paper explores new design methodologies for designing leakage tolerant digital architectures, based on architectural parameters like activity, logical depth, number of transitions for achieving a given task and total number of gates. Various architectures for a same logic function are compared at very low Vdd and VT that define the optimal total power consumption of each architecture. The first proposed design method selects the best architecture out of a set of architectures (baseline, sequential, parallel, pipelined, etc..) at optimal Vdd and threshold voltages, while a second design method takes as constraints given Vdd and threshold voltages.
Rue Jaquet-Droz 1
CH-2007 Neuchâtel , Switzerland,
Tel: 41 32 720 5111
Fax: 41 32 720 5763
Keynote by Peter A. BEEREL
"Asynchronous design for high-speed and low-power circuits"
Abstract - Asynchronous design is emerging as a practical alternative to synchronous design for both low power and high performance applications. Moreover, ASIC flows that support asynchronous design are becoming complete, including many that leverage existing front-end and back-end synchronous-oriented tools. This talk will review the different design styles and flows and highlight some of the on-going commercialization efforts in this area. Special attention will be paid to the single-track circuit families developed at USC that provide ultra high performance and low power characteristics. We will review the associated standard-cell libraries and flows that have been developed as well as the recent chip design efforts that demonstrate the benefits of this technology.
Peter A. Beerel
Associate Professor, EE/Systems
SITeC – Educational Programs
USC Viterbi School of Engineering
University of Southern California
3740 McClintock Avenue, EEB 350
Los Angeles, California 90089-2562
Tel: 213 740 4481
Fax: 213 740 9803
Keynote by Robin Wilson
"Design for Volume Manufacturing in the Deep Submicron Era"
Abstract - The deep sub-micron technologies of today present us with new opertunities and challanges. On one hand the level of integration and available process options enables the development of fully integrated high performance systems (digital,mixed signal and RF) , while on the other hand we have the challange of designing with increasing manufacturing variation and new electrical /reliability effects to consider. New design tools and methodologies are required. Looking to the past and even the present can give clues for the direction to take for the future. This talk , will describe through concrete examples the challenges overcome in developing design platforms for volume manufacture in the most recent technology nodes, including discussing the most imminent challanges to solve to maximise the benefit from forthcoming technologies.
Design Department Manager
850, rue Jean Monnet
38926 Crolles, France
Tel: 33 4 76 92 62 41