Best Paper Awards


  •  FPL 2010
    Barthe L., Benoit P., Torres L., “Investigation of a Masking Countermeasure against Side-Channel Attacks for RISC-based Processor Architectures”, IEEE FPL’10: Field Programmable Logic and Applications (2010), Italy, pp. 139-144 (nominated for the best paper award)
  • IEEE/IARIA International Conference on Advances in System Testing and Validation Lifecycle, Porto, Portugal, 20-25 Septembre 2009.
    J. Vial, A. Virazel, A. Bosio, L. Dilillo, P. Girard et S. Pravossoudovitch,
    Titre papier : “Using TMR Architectures for SoC yield Improvement”,
  • (Premium award) 2008 de la revue IET Computers and Digital Techniques
    Fully Digital Test Solution for a Set of ADCs and DACs Embedded in SiP or SoC
    V. Kerzérho, P. Cauvet, S. Bernard, F. Azaïs, M. Comte and M. Renovell
    Proc. IEE Computer & Digital Techniques, Published by The Institution of Engineering and Technology (IET), vol. 1, issue 3, May 2007, ISSN 17518601, pp. 146-153
    International Journal IET Computers & Digital Techniques 2007.
  • NASA/ESA AHS-2007 Conference on Adaptive Hardware and Systems.
    "PERPLEXUS: Pervasive Computing Framework for Modeling Complex Virtually-Unbounded Systems"
    Sanchez E., Perez-Uribe A., Thoma Y., Moreno J. M., Villa A., Napierlaski A., Sassatelli G., Lavarec E.
    NASA/ESA AHS-2007 Conference on Adaptive Hardware and Systems, pp. 587-591, 2007.
  • IEEE European Test Symposium 2006 (ETS’06).
    "Analogue Network of Converters: A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC"
    Azais F., Bernard S., Cauvet P., Comte M., Kerzérho V., Renovell M.
    IEEE European Test Symposium, May 21, pp. 159-164, 2006.
  • IEEE International Workshop on Electronics Design, Test & Applications 2006 (DELTA’06).
    "Electrical Behavior of GOS Fault Affected Domino Logic Cell Comte M."
    Ohtake S., Fujiwara H., Renovell M.
    IEEE International Workshop on Electronics DesignTest & Applications, January 17, pp. 183-189, 2006.
  • IEEE PhD Research in Microelectronics and Electronics (IEEE PRIME 2006).
    "How to Add the Integrity Checking Capability to Block Encryption Agorithms"
    Elbaz R., Torres L., Sassatelli G., Guillemin P., Bardouillet M., Rigaud J.B.
    IEEE Ph.D. Research in MicroElectronics and Electronics, pp. 369-372,(2006).
  • IEEE WOrkshop on Design and Diagnostics of Electronic Systems 2005 (DDECS’05).
    "Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic Solution"
    Badereddine N., Girard P., Pravossoudovitch S., Landrault C., Virazel A.
    IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 151-159, 2005.

Participation à la création d'entreprises
Lauréats du concours national d’aide à la création de technologies innovantes (OSEO) :