Friday, May 25
16:00-18:00
Registration
19:00-
Welcome reception
Saturday, May 26
7:30-8:00
8:00-8:15
Welcome Address (Hans-Joachim WUNDERLICH)
8:15-9:30
Each attendee introduces her/himself
9:30-10:30
Robust System Design: Overcoming Reliability Challenges
Subhasish MITRA (part I)
10:30-10:45
Coffee break
10:45-12:45
Subhasish MITRA (part II)
12:45-13:45
Lunch
13:45-15:15
Subhasish MITRA (part III)
15:15-15:30
15:30-16:30
Soft Errors: Sources and Mitigation, Dan ALEXANDRESCU (part I)
16:30-
Social Event
Sunday, May 27
8:00-10:00
Dan ALEXANDRESCU (part II)
10:00-10:15
10:15-11:15
Dan ALEXANDRESCU (part III)
11:15-12:45
Designing systems that are Dependable and Secure: Measurement, Analysis and Design, Ravishankar K. IYER (part I)
Ravishankar K. IYER (part II)
15:30-17:00
Ravishankar K. IYER (part III)
17:00-17:15
17:15-18:45
Validation and Fault Tolerance of Microprocessors
Jacob ABRAHAM (part I)
Social Dinner
Monday, May 28
8:00-9:45
Jacob ABRAHAM (part II)
9:45-10:00
10:00-11:30
Jacob ABRAHAM (part III)
11:30-12:00
Checkout
12:00-13:00
Track A
14:00-18:30
Dependable Processor Design, Peter HARROD
Track B
Hardware- and Software-Fault Tolerance, Design and Assessment of Dependable Computer Systems, Jean ARLAT